The present disclosure relates generally to semiconductor manufacturing, and more particularly, to integrated circuit devices and methods for forming such devices.
The semiconductor industry continues to have goals of higher density, superior performance, and lower cost. Scaling of device size has been a major tool user to reach these goals. However, scaling beyond the 100 nm process technology node has several difficulties associated with it, such as gate-oxide thickness, source and drain doping depths, and current density. These difficulties have resulted in new device structures to improve the existing metal oxide semiconductor field effect transistor (MOSFET) devices. Some of these new device structures include multi-gate MOSFET devices. A fin field effect transistor (FinFET) is a kind of multi-gate device which has a channel formed as a vertical fin. Multiple gates are formed over and along the sides of the vertical fin. A FinFET allows for a range of channel lengths and provides a broader process window for gate structures. A FinFET often includes high aspect-ratio semiconductor fins in which the channel and source/drain regions for the transistor are formed. The increased surface area of the channel and source/drain regions in a FinFET results in faster, more reliable and better-controlled semiconductor transistor devices. These advantages have found many new applications in various types of semiconductor devices.
A process for making a FinFET uses stringent process control, including in the area of contact landing. For example, contact holes need to overlay with thin vertical fin channels or raised source/drain well-pick-up lines. Process control for contact landing gets even more difficult when horizontal and vertical gate lines co-exist in multi-gate FinFET structures. In the metrology area, alignment marks and thickness monitor marks, among other metrology structures, may not be recognizable by metrology tools if these marks have the dimension of nanometers as a typical fin structure's lateral size. Therefore, it is preferable to create metrology marks by broadening the lateral fin dimensions on the existing fin layer without creating a new design layout, which is a highly resource intensive process few designers would invest in for a product.
As such, there is need for improved methods for forming alignment marks in a FinFET integrated circuitry in a flexible and cost effective way.